ArchLearn : Implementação de acelerador em hardware baseado em FPGA para redes neurais artificiais

Abstract

The need to run real-time and latency-sensitive systems has led to the development of a new paradigm in relation to dominant cloud computing, which is called edge computing. Thus, the new data distribution model seeks to bring the processing and treatment of data close to the edge of the network, a reason that leads to the development of platforms with low power processors close to sensors and mobile applications. Within this context, the growth in the use of Machine Learning algorithms and the possibility of transferring part of the execution of these models locally, opens up a range of questions regarding how to execute them efficiently. That said, this work implemented the convolution operation for an FPGA platform in order to optimize the execution time of a CNN (Convolutional Neural Network) in a microcontroller. The proposed approach was designed to perform in a specialized manner three convolutional layers of a CNN, which was trained to perform the classification of 10 classes of images present in the CIFAR-10 dataset. For comparison, two approaches were tested using an ARM CORTEX-M4 processor: without any software optimization and with optimization provided by special instructions SIMD (Single Instruction, Multiple Data) through the CMSIS-NN library. As a result, the execution time of the convolutional layers achieved in this work was up to 25% less than the fastest time using only the processor.