A comparative survey of ARM and RISC-V: architectures, applications and challenges

Abstract

The selection of a processor instruction set architecture (ISA) has become a foundational engineering decision that shapes the performance, power efficiency, security, and supply-chain independence of modern computing systems. Three converging trends make a renewed comparison of ARM and RISC-V especially timely: the expansion of computing into safety- and securitycritical domains governed by standards such as ISO 26262 and IEC 61508; the rise of RISC-V as the first credible open alternative to ARM, with over ten billion cores shipped by 2024; and the growing demand for hardware auditability following microarchitectural attacks such as Spectre and Meltdown and supply-chain compromises such as the XZ Utils backdoor. In this master’s thesis, we provide a comprehensive, parallel-structured comparative survey of the ARM and RISC-V architectures, spanning ISA design and evolution, microarchitecture, vector processing, and virtualization, together with the application domains of robotics, artificial intelligence, and hardware security — dimensions that existing ISA-level, benchmarking, and industry analyses address only in isolation. The work is an architectural survey rather than an experimental benchmarking study, grounded in ISA specifications, peer-reviewed literature from IEEE, ACM, USENIX, and Springer venues, vendor datasheets and safety documentation, and international functional-safety standards, and organised as a chapter-by-chapter parallel evaluation of the two architectures. The analysis finds that the gap between ARM and RISC-V is increasingly one of ecosystem maturity rather than architectural capability: ARM offers a vertically integrated, broadly deployed ecosystem with hardware-enforced security defaults (PAC, MTE, BTI, CCA) and certified safety cores, whereas RISC-V offers openness, amenability to formal verification, and license-free customisation, with ISO 26262 ASIL D cores now emerging. For artificial-intelligence workloads, RISC-V demonstrates up to fourfold superior energy efficiency through custom extensions, while ARM delivers up to fifteenfold faster inference on complex networks through a mature toolchain; these figures are best-case, implementation-dependent trends rather than fixed architectural verdicts. Across robotics and security, architecture selection proves application- and certificationdependent rather than absolute, and the frontier is shifting from a binary ARM-versus-RISC-V choice toward heterogeneous designs that compose both architectures with domain-specific accelerators on a single platform.